Résumé:
Flash memories have attracted considerable attention as promising next-generation nonvolatile memories owing to their higher chip density, multi-bit per cell storage property and compatibility with the current complementary metal-oxide-semiconductor (CMOS) process. Flash memories have been fabricated through microcontact printing methods. Fabrication through solution process enables large-scale roll-to-roll printing of memories, leading to innovative applications in modern electronics. Among various device configurations of flash memories, floating gate architecture is considered as a promising candidate to realize the ultimate goal of flash memory due to its non-destructive read-out and compatibility with complementary CMOS devices. Floating gate transistor memories embedded with hybrid nanostructures at the gate dielectrics is a way to replace planar floating gate for meeting the requirement of long retention time with high density data storage for the next generation flash memories. However, poor charge retention time induced by the thin tunneling dielectric layer is a drawback for the floating gate memory device. By simply increasing the thickness of tunneling dielectric layer would degrade the program/erase speed and increase the power consumption. On this regard, we present a self-assembly approach for constructing monolayers of nanostructures to achieve better charge retention properties.

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